Personnel

FICs - Prof. Philip K. T. Mok

Description

In the past few years, the rapid growth of the ultra-thin, ultra-light weight portable mobile devices market, like iPhones and android phones, drive the great demand of system-on-a-chip (SoC) design with increasing number of systems integrated onto a single chip. In order to prolong the battery life of the portable devices, the power supply voltages of some of the logic circuits need to scale down to sub-threshold or near the threshold voltage of the transistor to reduce the power consumption of the SoC, especially in idling and standby mode. Therefore, there is an urgent need to provide a tunable supply voltage for very low-power VLSI circuit down to 0.5V in future SoC design. The design and implementation of the required power management unit which control the supply voltages of different components inside the SoC becomes very challenging. Low-dropout linear regulator (LDO) is one of key building blocks of the power management unit. Nowadays, there are more than 20 LDOs inside the power management unit to provide different supply voltages to various components inside the SoC. The power efficiency, dropout voltage, transient response time, and chip area are the major concerns in designing the LDO. With down to 0.5-V supply voltage, the conventional LDO with analog feedback control loop will not function very well. In addition, in the future SoC design, advanced CMOS technologies below 65nm will be used and these short-channel transistors make analog circuit design very difficult. Therefore, digital LDO have been proposed in the recent years to target for this problem. Digital LDO is a LDO with a digital controlled loop instead of the analog controlled loop used in the conventional LDO. However, existing digital LDOs are not as well-developed as the analog LDOs and the performance of these digital LDOs are not optimized. One of the major issues of the existing digital LDO is the slow transient response time and large quiescent current consumption. Due to the slow transient response, the use of digital LDO in power management circuits is limited. Thus the objective of this proposal is to develop a low-power fast-transient digital LDO for SoC applications. The focus will be on how to speed up the transient response of the digital LDO without using large quiescent current. Other issues related to digital LDO performance such as stability, minimum dropout voltage, startup sequence, short-circuit protection, chip area consumption, etc. will also be explored in this project.

Source: RGC | ITF