Personnel

FICs - Prof. Philip K. T. Mok

Description

Over a decade of rapid expansion later, the market of smart devices is expected to continue growing and the current trend is to create even more compact designs. In this trend, numerous discrete modules are integrated on a single chip into what is known as a system-on-a-chip (SoC). A practical SoC usually enters the idle mode by lowering the supply voltage, which even though can effectively extend the battery lifetime, poses challenges to circuit operation. When the supply voltage converted from the battery by a switching (buck) converter is ultralow (e.g., 0.5 V), the low dropout regulators (LDRs), which are essential to generate the finely regulated supply from a noisy output rail, are unable to adequately reject the noise from its input. Such low-voltage, low-current LDRs are said to be working in the retention mode. The poor power supply rejection (PSR) will render the SoC vulnerable to switching noise from the buck converter. Conventional techniques improve the PSR by boosting the loop gain or bandwidth for noise suppression, or using a feed-forward path for supply noise cancellation. Such techniques require either a sufficiently high supply voltage or an expensive power budget, which is not available in retention mode operation. Therefore, methods of enhancing the PSR especially for retention mode LDRs must be developed. This proposed project will come up with a new design of the analog/digital hybrid control-based LDR with enhanced PSR over a frequency range of tens of megahertz. The hybrid scheme inherits the merits of higher accuracy and insensitivity to power supply noise from the analog control, and the advantages of low supply voltage operation and faster response under a low power budget from the digital control. In particular, two variations, namely the analog-assisted digital controller and the digital-assisted analog controller, will be developed and compared to gain insights for designing the proposed retention mode LDR. Furthermore, a comprehensive analysis on the stability of the main and auxiliary regulation loops will be conducted to motivate both hybrid designs. This project will also try to reduce power consumption further with ultra-low-power applications in mind, as well as implementing a two-step power conversion system. The high PSR LDR will be characterized in various real application scenarios for a complete evaluation of the proposed PSR enhancement techniques developed in this project.

Source: RGC | ITF